The present disclosure relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device.
In the case of a semiconductor memory device, such as in a silicon storage technology (SST) flash non-volatile memory (NVM) cell, a problem arises in that cell size becomes large while forming a gate electrode.
FIG. 1 is a cross-sectional view showing a gate structure of a semiconductor memory device.
Referring to FIG. 1, a gate dielectric layer 11 is formed on a semiconductor substrate 10 on which source and drain areas (not shown) are formed, and a floating gate 12 is formed over a portion of the area over the gate dielectric layer 11.
A control gate 13 is formed on the other area of the gate dielectric layer 11 and over a portion of the floating gate 12.
A dielectric layer 14 is formed over the floating gate 12 and the control gate 13, including the area between the floating gate 12 and the control gate 13, thereby completing the gate structure as shown in FIG. 1.
FIG. 1 is a cross-sectional view so that it is difficult to sort the shape of the floating gate 12. Though not clearly shown in the drawing, the floating gate 12 of the related art is formed in a plate shape that is a dish shape whose center is concave.
In order to make the plate shape whose center is concave as described above, the floating gate 12 is formed through a local oxidation of silicon (LOCOS) process, including an oxidation process and an annealing process on one surface thereof.
Therefore, as shown in FIG. 1, the floating gate 12 is formed to be larger than needed for its function by a length L in the side direction. Such a structure restricts device density as the size of the semiconductor memory device becomes more miniaturized.